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-rw-r--r--PIC/stack.vhd51
1 files changed, 0 insertions, 51 deletions
diff --git a/PIC/stack.vhd b/PIC/stack.vhd
deleted file mode 100644
index fd376c0..0000000
--- a/PIC/stack.vhd
+++ /dev/null
@@ -1,51 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-entity stack is
- generic (
- DEPTH : positive := 8;
- WIDTH : positive := 13
- );
- port (
- clk : in std_logic;
- reset : in std_logic;
- push : in std_logic;
- pop : in std_logic;
- din : in std_logic_vector(WIDTH - 1 downto 0);
- dout : out std_logic_vector(WIDTH - 1 downto 0)
- );
-end entity stack;
-
-architecture rtl of stack is
-
- type stack_t is
- array (0 to DEPTH - 1)
- of std_logic_vector(WIDTH - 1 downto 0);
-
- signal mem : stack_t
- := (others => (others => '0'));
-
- -- write pointer
- signal top : unsigned(2 downto 0)
- := (others => '0');
-begin
-
- dout <=
- mem(to_integer(top - 1)) when top /= 0 else (others => '0');
-
- stck : process(clk, reset)
- begin
- if reset = '1' then
- top <= (others => '0');
- elsif rising_edge(clk) then
- if push = '1' then
- mem(to_integer(top)) <= din;
- top <= top + 1;
- elsif pop = '1' then
- top <= top - 1;
- end if;
- end if;
- end process;
-
-end architecture rtl;