diff options
Diffstat (limited to 'hdl/PIC.vhd')
| -rw-r--r-- | hdl/PIC.vhd | 93 |
1 files changed, 86 insertions, 7 deletions
diff --git a/hdl/PIC.vhd b/hdl/PIC.vhd index a31bec7..7471add 100644 --- a/hdl/PIC.vhd +++ b/hdl/PIC.vhd @@ -22,7 +22,10 @@ entity PIC is -- UART physical pins uart_tx : out std_logic; - uart_rx : in std_logic + uart_rx : in std_logic; + + -- 1-Wire physical pin + ow_pin : inout std_logic ); end entity PIC; @@ -34,12 +37,13 @@ architecture rtl of PIC is signal alu_skip : std_logic; signal mem_q : std_logic_vector(7 downto 0); - signal mem_qstatus : std_logic_vector(2 downto 0); + signal mem_qstatus : std_logic_vector(7 downto 0); signal mem_we : std_logic; signal mem_re : std_logic; signal bit_select : std_logic_vector(2 downto 0); signal addr : std_logic_vector(6 downto 0); + signal mem_addr : std_logic_vector(7 downto 0); signal sm_data : std_logic_vector(7 downto 0); signal sm_pc : std_logic_vector(12 downto 0); signal we_w : std_logic; @@ -64,6 +68,26 @@ architecture rtl of PIC is signal uart_rx_empty : std_logic; signal uart_rx_full : std_logic; + -- 1-Wire <-> dpram bridge signals + signal ow_tx_byte : std_logic_vector(7 downto 0); + signal ow_op : std_logic_vector(1 downto 0); + signal ow_start : std_logic; + signal ow_rx_byte : std_logic_vector(7 downto 0); + signal ow_presence : std_logic; + signal ow_busy : std_logic; + + -- Interrupt bridge signals + signal irq_pending : std_logic; + signal gie_clear : std_logic; + signal gie_set : std_logic; + + -- Timer0 bridge signals + signal t0if : std_logic; + signal tmr0_val : std_logic_vector(7 downto 0); + signal tmr0_we_sig : std_logic; + signal tmr0_in_sig : std_logic_vector(7 downto 0); + signal option_reg : std_logic_vector(7 downto 0); + begin work_reg <= W; @@ -71,6 +95,9 @@ begin instruction_return <= instr_ret; status <= alu_status; + -- banking: RP0 (STATUS bit 5) selects bank 0 or bank 1 + mem_addr <= mem_qstatus(5) & addr; + b_operand_select : process(use_literal, sm_data, mem_q) begin if use_literal = '1' then @@ -110,7 +137,10 @@ begin stack_din => stack_din, stack_dout => stack_dout, alu_skip => alu_skip, - alu_result => alu_result + alu_result => alu_result, + irq_pending => irq_pending, + gie_clear => gie_clear, + gie_set => gie_set ); alu : entity work.alu(rtl) @@ -119,7 +149,7 @@ begin b => b_operand, op => alu_operation, bit_select => bit_select, - status_in => mem_qstatus, + status_in => mem_qstatus(2 downto 0), result => alu_result, status => alu_status, skip => alu_skip @@ -136,14 +166,14 @@ begin ); mem : entity work.dpram(rtl) - generic map (DEPTH => 128) + generic map (DEPTH => 256) port map ( clk => clk, we => mem_we, re => mem_re, d => alu_result, d_status => "00000" & alu_status, - addr => addr, + addr => mem_addr, q => mem_q, q_status => mem_qstatus, port_a => port_a, @@ -155,7 +185,56 @@ begin uart_rx_byte => uart_rx_byte, uart_rx_rd_en => uart_rx_rd_en, uart_rx_empty => uart_rx_empty, - uart_rx_full => uart_rx_full + uart_rx_full => uart_rx_full, + ow_tx_byte => ow_tx_byte, + ow_op => ow_op, + ow_start => ow_start, + ow_rx_byte => ow_rx_byte, + ow_presence => ow_presence, + ow_busy => ow_busy, + tmr0_val => tmr0_val, + tmr0_we => tmr0_we_sig, + tmr0_in => tmr0_in_sig, + option_reg => option_reg, + t0if_set => t0if, + gie_clear => gie_clear, + gie_set => gie_set, + irq_pending => irq_pending + ); + + ow_inst : entity work.onewire + generic map ( + CLK_FREQ => CLK_FREQ + ) + port map ( + clk => clk, + reset => reset, + ow_pin => ow_pin, + start => ow_start, + op => ow_op, + tx_byte => ow_tx_byte, + rx_byte => ow_rx_byte, + presence => ow_presence, + busy => ow_busy, + done => open + ); + + tmr0_inst : entity work.timer0(rtl) + generic map ( + CLK_FREQ => CLK_FREQ + ) + port map ( + clk => clk, + reset => reset, + t0cki => '0', + t0cs => option_reg(5), + t0se => option_reg(4), + psa => option_reg(3), + ps => option_reg(2 downto 0), + tmr0_we => tmr0_we_sig, + tmr0_in => tmr0_in_sig, + tmr0_out => tmr0_val, + t0if => t0if ); uart_inst : entity work.uart |