diff options
Diffstat (limited to 'hdl')
| -rw-r--r-- | hdl/hexfile_reader.vhd | 2 | ||||
| -rw-r--r-- | hdl/prog_rom.v | 30 | ||||
| -rw-r--r-- | hdl/rom.py | 18 |
3 files changed, 19 insertions, 31 deletions
diff --git a/hdl/hexfile_reader.vhd b/hdl/hexfile_reader.vhd index 143a264..8c38ff4 100644 --- a/hdl/hexfile_reader.vhd +++ b/hdl/hexfile_reader.vhd @@ -29,7 +29,7 @@ PACKAGE read_intel_hex_pack IS CONSTANT Inst_bits : INTEGER := 14; CONSTANT data_bits : INTEGER := 8; - CONSTANT inst_mem_size : INTEGER := 1024; + CONSTANT inst_mem_size : INTEGER := 4096; TYPE program_array IS ARRAY (0 TO inst_mem_size-1) OF STD_LOGIC_VECTOR(Inst_bits-1 DOWNTO 0); ------------------------------------------------------------------------------ diff --git a/hdl/prog_rom.v b/hdl/prog_rom.v index 03b8d9e..ae35289 100644 --- a/hdl/prog_rom.v +++ b/hdl/prog_rom.v @@ -1,31 +1,26 @@ /* Generated by Yosys 0.63+89 (git sha1 de99d67bb, clang++ 18.1.8 -fPIC -O3) */ (* top = 0 *) -(* src = "/workspace/hdl/rom.py:39" *) +(* src = "/workspace/hdl/rom.py:34" *) (* generator = "Amaranth" *) -module prog_rom(addr, \clk$3 , rst, data, clk); - (* src = "/workspace/hdl/rom.py:42" *) - input [12:0] addr; - wire [12:0] addr; +module prog_rom(clk, rst, data, addr); (* src = "/usr/local/lib/python3.11/dist-packages/amaranth/hdl/_ir.py:283" *) - input \clk$3 ; - wire \clk$3 ; + input clk; + wire clk; (* src = "/usr/local/lib/python3.11/dist-packages/amaranth/hdl/_ir.py:283" *) input rst; wire rst; - (* src = "/workspace/hdl/rom.py:46" *) + (* src = "/workspace/hdl/rom.py:40" *) output [13:0] data; wire [13:0] data; - (* src = "/workspace/hdl/rom.py:41" *) - input clk; - wire clk; - (* src = "/usr/local/lib/python3.11/dist-packages/amaranth/hdl/_ir.py:283" *) - wire \clk$7 ; - (* src = "/workspace/hdl/rom.py:46" *) + (* src = "/workspace/hdl/rom.py:36" *) + input [12:0] addr; + wire [12:0] addr; + (* src = "/workspace/hdl/rom.py:40" *) wire [11:0] mem_r_addr; - (* src = "/workspace/hdl/rom.py:46" *) + (* src = "/workspace/hdl/rom.py:40" *) wire [13:0] mem_r_data; - (* src = "/workspace/hdl/rom.py:45" *) + (* src = "/workspace/hdl/rom.py:39" *) reg [13:0] \U$0 [4095:0]; initial begin \U$0 [0] = 14'h0000; @@ -4126,11 +4121,10 @@ module prog_rom(addr, \clk$3 , rst, data, clk); \U$0 [4095] = 14'h0000; end reg [13:0] _0_; - always @(posedge \clk$3 ) begin + always @(posedge clk) begin _0_ <= \U$0 [addr[11:0]]; end assign data = _0_; assign mem_r_addr = addr[11:0]; assign mem_r_data = data; - assign \clk$7 = \clk$3 ; endmodule @@ -1,20 +1,15 @@ #!/usr/bin/env python3 """ -Convert an Intel HEX file to a Verilog ROM module using Amaranth. -Usage: - python3 hex2rom_amaranth.py program.hex > prog_rom.v -Produces a module 'prog_rom' with: - input clk, input [12:0] addr, output [13:0] data -Depth defaults to 4096 (8192/2). +Make the correct ROM using Amaranth into Verilog. """ import sys import argparse from amaranth import * from amaranth.back import verilog -DEPTH = 8192 // 2 +DEPTH = 4096 DATA_WIDTH = 14 -ADDR_WIDTH = 13 # external addr width +ADDR_WIDTH = 13 def parse_ihex(path): words = [0] * DEPTH @@ -38,7 +33,6 @@ def parse_ihex(path): def make_rom_module(words): m = Module() - clk = Signal() addr = Signal(ADDR_WIDTH) data = Signal(DATA_WIDTH) @@ -51,11 +45,11 @@ def make_rom_module(words): data.eq(rd.data) ] - return m, clk, addr, data + return m, addr, data def render_verilog(words, module_name="prog_rom"): - m, clk, addr, data = make_rom_module(words) - v = verilog.convert(m, ports=[clk, addr, data], name=module_name) + m, addr, data = make_rom_module(words) + v = verilog.convert(m, ports=[addr, data], name=module_name) return v.replace("(* top = 1 *)\n", "(* top = 0 *)\n") class ComponentWrapper(Elaboratable): |