diff options
Diffstat (limited to 'hex2rom.py')
| -rw-r--r-- | hex2rom.py | 12 |
1 files changed, 10 insertions, 2 deletions
@@ -43,6 +43,7 @@ def render(words): lines.append(f' DEPTH : positive := {DEPTH}') lines.append(' );') lines.append(' port (') + lines.append(' clk : in std_logic;') lines.append(' addr : in std_logic_vector(12 downto 0);') lines.append(' data : out std_logic_vector(13 downto 0)') lines.append(' );') @@ -50,14 +51,21 @@ def render(words): lines.append('') lines.append('architecture rtl of prog_rom is') lines.append(f' type rom_t is array (0 to {DEPTH} - 1) of std_logic_vector(13 downto 0);') - lines.append(' constant rom : rom_t := (') + lines.append(' signal rom : rom_t := (') for i, w in enumerate(words): bits = format(w, f'014b') sep = ',' if i < DEPTH - 1 else ' ' lines.append(f' {i:4d} => "{bits}"{sep}') lines.append(' );') + lines.append(' attribute ram_style : string;') + lines.append(' attribute ram_style of rom : signal is "block";') lines.append('begin') - lines.append(' data <= rom(to_integer(unsigned(addr(9 downto 0))));') + lines.append(' process(clk)') + lines.append(' begin') + lines.append(' if rising_edge(clk) then') + lines.append(' data <= rom(to_integer(unsigned(addr(9 downto 0))));') + lines.append(' end if;') + lines.append(' end process;') lines.append('end architecture rtl;') return '\n'.join(lines) + '\n' |