| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | remove redundant clock input from verilog generator | Väinö Kauppila | 2026-04-20 | 3 | -31/+19 |
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| * | prog rom generation using Amaranth | Väinö Kauppila | 2026-04-20 | 7 | -66/+4279 |
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| * | interrupts working now with timer | Väinö Kauppila | 2026-04-19 | 2 | -3/+3 |
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| * | BSRAM progmem. fix Makefile memory command that does not work. add ↵ | Väinö Kauppila | 2026-04-19 | 10 | -42/+563 |
| | | | | | interrupts, bank 1, timer0. Timer0 not tested. | ||||
| * | refactor dir structure, add fib.c | Vaino Kauppila | 2026-04-19 | 14 | -0/+1874 |
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index : vhdl_pic | |
| PIC16F84-compatible CPU in VHDL on a Tang Primer 25K. Plays snake. | root |
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