From eb8643ddbef43547eb7bfe58789a3908926c7258 Mon Sep 17 00:00:00 2001
From: Vaino Kauppila <vaino@vke.fi>
Date: Sun, 19 Apr 2026 12:32:58 +0300
Subject: refactor dir structure, add fib.c

---
 Makefile.inner | 96 +++++++++++++++++++++++++++++-----------------------------
 1 file changed, 48 insertions(+), 48 deletions(-)

(limited to 'Makefile.inner')

diff --git a/Makefile.inner b/Makefile.inner
index 3184cc3..957843c 100644
--- a/Makefile.inner
+++ b/Makefile.inner
@@ -1,4 +1,5 @@
-PIC_DIR = PIC
+HDL_DIR = hdl
+BUILD   = build
 
 DEVICE  = GW5A-LV25MG121NES
 FAMILY  = GW5A-25A
@@ -10,72 +11,71 @@ STD     = --std=08
 
 # Synthesizable sources (no testbenches, no VHDL file-I/O packages)
 SYN_FILES = \
-	$(PIC_DIR)/common.vhd \
-	$(PIC_DIR)/decoder.vhd \
-	$(PIC_DIR)/fifo.vhd \
-	$(PIC_DIR)/uart.vhd \
-	$(PIC_DIR)/ALU.vhd \
-	$(PIC_DIR)/stack.vhd \
-	$(PIC_DIR)/dpram.vhd \
-	$(PIC_DIR)/state_machine.vhd \
-	$(PIC_DIR)/PIC.vhd \
-	$(PIC_DIR)/prog_rom.vhd \
-	$(PIC_DIR)/pic_top.vhd
+	$(HDL_DIR)/common.vhd \
+	$(HDL_DIR)/decoder.vhd \
+	$(HDL_DIR)/fifo.vhd \
+	$(HDL_DIR)/uart.vhd \
+	$(HDL_DIR)/ALU.vhd \
+	$(HDL_DIR)/stack.vhd \
+	$(HDL_DIR)/dpram.vhd \
+	$(HDL_DIR)/state_machine.vhd \
+	$(HDL_DIR)/PIC.vhd \
+	$(HDL_DIR)/prog_rom.vhd \
+	$(HDL_DIR)/pic_top.vhd
 
 # Simulation adds the hex-reader package and testbenches
 SIM_FILES = \
-	$(PIC_DIR)/common.vhd \
-	$(PIC_DIR)/decoder.vhd \
-	$(PIC_DIR)/hexfile_reader.vhd \
-	$(PIC_DIR)/fifo.vhd \
-	$(PIC_DIR)/uart.vhd \
-	$(PIC_DIR)/ALU.vhd \
-	$(PIC_DIR)/stack.vhd \
-	$(PIC_DIR)/dpram.vhd \
-	$(PIC_DIR)/state_machine.vhd \
-	$(PIC_DIR)/PIC.vhd
+	$(HDL_DIR)/common.vhd \
+	$(HDL_DIR)/decoder.vhd \
+	$(HDL_DIR)/hexfile_reader.vhd \
+	$(HDL_DIR)/fifo.vhd \
+	$(HDL_DIR)/uart.vhd \
+	$(HDL_DIR)/ALU.vhd \
+	$(HDL_DIR)/stack.vhd \
+	$(HDL_DIR)/dpram.vhd \
+	$(HDL_DIR)/state_machine.vhd \
+	$(HDL_DIR)/PIC.vhd
 
 TB_FILES = \
-	$(PIC_DIR)/tb_stack.vhd \
-	$(PIC_DIR)/tb_pic.vhd
+	$(HDL_DIR)/tb_stack.vhd \
+	$(HDL_DIR)/tb_pic.vhd
 
-all: $(TOP).fs
+all: $(BUILD)/$(TOP).fs
+
+$(BUILD):
+	mkdir -p $@
 
 # Synthesize
-$(TOP).json: $(SYN_FILES)
-	ghdl -a $(STD) $(SYN_FILES)
-	yosys $(MODULE) -p "ghdl $(STD) $(TOP); memory_map; synth_gowin -json $@ -family gw5a"
+$(BUILD)/$(TOP).json: $(SYN_FILES) | $(BUILD)
+	ghdl -a $(STD) --workdir=$(BUILD) $(SYN_FILES)
+	yosys $(MODULE) -p "ghdl $(STD) --workdir=$(BUILD) $(TOP); memory_map; synth_gowin -json $@ -family gw5a"
 
 # Place and route
-$(TOP)_pnr.json: $(TOP).json $(CST)
+$(BUILD)/$(TOP)_pnr.json: $(BUILD)/$(TOP).json $(CST)
 	nextpnr-himbaechel --json $< --write $@ \
 		--device $(DEVICE) --vopt family=GW5A-25A --vopt cst=$(CST) \
-		--vopt sspi_as_gpio --freq 50 --report $(TOP)_timing.json
+		--vopt sspi_as_gpio --freq 50 --report $(BUILD)/$(TOP)_timing.json
 
 # Pack bitstream
-$(TOP).fs: $(TOP)_pnr.json
+$(BUILD)/$(TOP).fs: $(BUILD)/$(TOP)_pnr.json
 	gowin_pack --sspi_as_gpio --cpu_as_gpio -d $(FAMILY) -o $@ $<
 
-sim: $(SIM_FILES) $(TB_FILES)
-	ghdl -a $(STD) $(SIM_FILES) $(TB_FILES)
-	ghdl -e $(STD) tb_stack
-	ghdl -r $(STD) tb_stack
-	ghdl -e $(STD) tb_pic
-	ghdl -r $(STD) tb_pic --vcd=tb_pic.vcd
+sim: $(SIM_FILES) $(TB_FILES) | $(BUILD)
+	ghdl -a $(STD) --workdir=$(BUILD) $(SIM_FILES) $(TB_FILES)
+	ghdl -e $(STD) --workdir=$(BUILD) -o $(BUILD)/tb_stack tb_stack
+	ghdl -r $(STD) --workdir=$(BUILD) tb_stack
+	ghdl -e $(STD) --workdir=$(BUILD) -o $(BUILD)/tb_pic tb_pic
+	ghdl -r $(STD) --workdir=$(BUILD) tb_pic --vcd=$(BUILD)/tb_pic.vcd
 
-pic_top.dot: $(SYN_FILES)
-	ghdl -a $(STD) $(SYN_FILES)
-	yosys $(MODULE) -p "ghdl $(STD) $(TOP); show -format dot -prefix pic_top"
+$(BUILD)/pic_top.dot: $(SYN_FILES) | $(BUILD)
+	ghdl -a $(STD) --workdir=$(BUILD) $(SYN_FILES)
+	yosys $(MODULE) -p "ghdl $(STD) --workdir=$(BUILD) $(TOP); show -format dot -prefix $(BUILD)/pic_top"
 
-uart.dot: $(PIC_DIR)/fifo.vhd $(PIC_DIR)/uart.vhd
-	ghdl -a $(STD) $(PIC_DIR)/fifo.vhd $(PIC_DIR)/uart.vhd
-	yosys $(MODULE) -p "ghdl $(STD) uart; show -format dot -prefix uart"
+$(BUILD)/uart.dot: $(HDL_DIR)/fifo.vhd $(HDL_DIR)/uart.vhd | $(BUILD)
+	ghdl -a $(STD) --workdir=$(BUILD) $(HDL_DIR)/fifo.vhd $(HDL_DIR)/uart.vhd
+	yosys $(MODULE) -p "ghdl $(STD) --workdir=$(BUILD) uart; show -format dot -prefix $(BUILD)/uart"
 
 clean:
-	rm -f $(TOP).json $(TOP)_pnr.json $(TOP).fs $(TOP)_timing.json
-	rm -f pic_top.dot uart.dot
-	rm -f *.o work-obj08.cf e~*.lst
-	rm -f *.vcd
-	rm -f tb_pic tb_stack
+	rm -rf $(BUILD)
 
 .PHONY: all sim clean
-- 
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