From 129a1c975dbd0c042576010b1f6eb40d19fc5733 Mon Sep 17 00:00:00 2001 From: Vaino Kauppila Date: Sun, 19 Apr 2026 03:02:33 +0300 Subject: fix operand order of subtraction. add rollover counter UART test. --- PIC/ALU.vhd | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) (limited to 'PIC/ALU.vhd') diff --git a/PIC/ALU.vhd b/PIC/ALU.vhd index ac770a6..b7c0344 100644 --- a/PIC/ALU.vhd +++ b/PIC/ALU.vhd @@ -78,7 +78,11 @@ architecture rtl of alu is end if; res <= t; if do_skip then - do_skip_out <= '1' when unsigned(t) = 0 else '0'; + if unsigned(t) = 0 then + do_skip_out <= '1'; + else + do_skip_out <= '0'; + end if; else stat <= set_flag(FLAG_Z, sel(unsigned(t) = 0, '1', '0'), stat_in); end if; @@ -117,10 +121,11 @@ begin result <= tmp_extended(7 downto 0); when SUBLW | SUBWF => - tmp_extended := std_logic_vector(unsigned('0' & a) - unsigned('0' & b)); + -- PIC16F84A: SUBWF = f - W, SUBLW = k - W → dest = b - a + tmp_extended := std_logic_vector(unsigned('0' & b) - unsigned('0' & a)); - -- DC - tmp(4 downto 0) := std_logic_vector(('0' & unsigned(a(3 downto 0))) - ('0' & unsigned(b(3 downto 0)))); + -- DC: borrow out of lower nibble + tmp(4 downto 0) := std_logic_vector(('0' & unsigned(b(3 downto 0))) - ('0' & unsigned(a(3 downto 0)))); tmp_status := set_flag(FLAG_Z, sel(unsigned(tmp_extended(7 downto 0)) = 0, '1', '0'), status_in); tmp_status := set_flag(FLAG_C, not tmp_extended(8), tmp_status); -- cgit v1.3