From 8bd8dd6ce07fb8e247f651b3c61c94bb1f00895a Mon Sep 17 00:00:00 2001 From: Väinö Kauppila Date: Sun, 19 Apr 2026 00:33:08 +0300 Subject: starting files and example programs --- PIC/stack.vhd | 51 +++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 51 insertions(+) create mode 100644 PIC/stack.vhd (limited to 'PIC/stack.vhd') diff --git a/PIC/stack.vhd b/PIC/stack.vhd new file mode 100644 index 0000000..fd376c0 --- /dev/null +++ b/PIC/stack.vhd @@ -0,0 +1,51 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity stack is + generic ( + DEPTH : positive := 8; + WIDTH : positive := 13 + ); + port ( + clk : in std_logic; + reset : in std_logic; + push : in std_logic; + pop : in std_logic; + din : in std_logic_vector(WIDTH - 1 downto 0); + dout : out std_logic_vector(WIDTH - 1 downto 0) + ); +end entity stack; + +architecture rtl of stack is + + type stack_t is + array (0 to DEPTH - 1) + of std_logic_vector(WIDTH - 1 downto 0); + + signal mem : stack_t + := (others => (others => '0')); + + -- write pointer + signal top : unsigned(2 downto 0) + := (others => '0'); +begin + + dout <= + mem(to_integer(top - 1)) when top /= 0 else (others => '0'); + + stck : process(clk, reset) + begin + if reset = '1' then + top <= (others => '0'); + elsif rising_edge(clk) then + if push = '1' then + mem(to_integer(top)) <= din; + top <= top + 1; + elsif pop = '1' then + top <= top - 1; + end if; + end if; + end process; + +end architecture rtl; -- cgit v1.3