From 9dd09eaa88df41057700e59d9abe83fd204f1215 Mon Sep 17 00:00:00 2001 From: Väinö Kauppila Date: Mon, 20 Apr 2026 18:45:38 +0300 Subject: remove redundant clock input from verilog generator --- hdl/hexfile_reader.vhd | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'hdl/hexfile_reader.vhd') diff --git a/hdl/hexfile_reader.vhd b/hdl/hexfile_reader.vhd index 143a264..8c38ff4 100644 --- a/hdl/hexfile_reader.vhd +++ b/hdl/hexfile_reader.vhd @@ -29,7 +29,7 @@ PACKAGE read_intel_hex_pack IS CONSTANT Inst_bits : INTEGER := 14; CONSTANT data_bits : INTEGER := 8; - CONSTANT inst_mem_size : INTEGER := 1024; + CONSTANT inst_mem_size : INTEGER := 4096; TYPE program_array IS ARRAY (0 TO inst_mem_size-1) OF STD_LOGIC_VECTOR(Inst_bits-1 DOWNTO 0); ------------------------------------------------------------------------------ -- cgit v1.3