From 9dd09eaa88df41057700e59d9abe83fd204f1215 Mon Sep 17 00:00:00 2001 From: Väinö Kauppila Date: Mon, 20 Apr 2026 18:45:38 +0300 Subject: remove redundant clock input from verilog generator --- hdl/rom.py | 18 ++++++------------ 1 file changed, 6 insertions(+), 12 deletions(-) (limited to 'hdl/rom.py') diff --git a/hdl/rom.py b/hdl/rom.py index d370e7d..2339cb4 100644 --- a/hdl/rom.py +++ b/hdl/rom.py @@ -1,20 +1,15 @@ #!/usr/bin/env python3 """ -Convert an Intel HEX file to a Verilog ROM module using Amaranth. -Usage: - python3 hex2rom_amaranth.py program.hex > prog_rom.v -Produces a module 'prog_rom' with: - input clk, input [12:0] addr, output [13:0] data -Depth defaults to 4096 (8192/2). +Make the correct ROM using Amaranth into Verilog. """ import sys import argparse from amaranth import * from amaranth.back import verilog -DEPTH = 8192 // 2 +DEPTH = 4096 DATA_WIDTH = 14 -ADDR_WIDTH = 13 # external addr width +ADDR_WIDTH = 13 def parse_ihex(path): words = [0] * DEPTH @@ -38,7 +33,6 @@ def parse_ihex(path): def make_rom_module(words): m = Module() - clk = Signal() addr = Signal(ADDR_WIDTH) data = Signal(DATA_WIDTH) @@ -51,11 +45,11 @@ def make_rom_module(words): data.eq(rd.data) ] - return m, clk, addr, data + return m, addr, data def render_verilog(words, module_name="prog_rom"): - m, clk, addr, data = make_rom_module(words) - v = verilog.convert(m, ports=[clk, addr, data], name=module_name) + m, addr, data = make_rom_module(words) + v = verilog.convert(m, ports=[addr, data], name=module_name) return v.replace("(* top = 1 *)\n", "(* top = 0 *)\n") class ComponentWrapper(Elaboratable): -- cgit v1.3