From c9d20884c0a71eb80340f33e58aa73ad99f45ce2 Mon Sep 17 00:00:00 2001 From: Väinö Kauppila Date: Mon, 20 Apr 2026 19:44:19 +0300 Subject: try fix the snake bug --- hdl/tb_pic.vhd | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) (limited to 'hdl/tb_pic.vhd') diff --git a/hdl/tb_pic.vhd b/hdl/tb_pic.vhd index 2b6f722..75f385c 100644 --- a/hdl/tb_pic.vhd +++ b/hdl/tb_pic.vhd @@ -4,6 +4,10 @@ use ieee.numeric_std.all; use work.read_intel_hex_pack.all; entity tb_pic is + generic ( + CLK_FREQ : positive := 50_000_000; -- 50M, GW5A clock + BAUD_RATE : positive := 115_200 + ); end entity tb_pic; architecture behavioural of tb_pic is @@ -29,6 +33,10 @@ architecture behavioural of tb_pic is -- program memory: 1024 x 14-bit signal prog_mem : program_array := (others => (others => '0')); + signal byte_in : std_logic_vector(7 downto 0); + signal tx_should_send : std_logic; + + begin clk <= not clk after T_clk / 2 when not done else unaffected; @@ -53,6 +61,27 @@ begin uart_rx => uart_rx ); + tx_should_send <= '1'; + byte_in <= x"FC"; + + uart_master: entity work.uart + generic map ( + CLK_FREQ => CLK_FREQ, + BAUD_RATE => BAUD_RATE, + CLKS_PER_BIT => CLK_FREQ / BAUD_RATE) + port map ( + clk => clk, + tx_should_send => tx_should_send, + byte_in => byte_in, + tx_done => open, + baud_tick => open, + uart_tx => uart_rx, + uart_rx => uart_tx, + rd_en => '0', + rx_data => open, + rx_empty => open, + rx_full => open); + stimulus : process is variable mem : program_array; begin -- cgit v1.3