library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

-- FPGA top-level for the Tang Primer 25K (GW5A-LV25MG121).
-- Pin assignments live in primer25k.cst.
-- The prog_rom entity holds the compiled program; swap its 'rom' constant
-- to deploy a new program without changing anything else.

entity pic_top is
  port (
    clk          : in    std_logic;     -- 50 MHz board clock (E2)
    reset_btn    : in    std_logic;  -- H11 user button, active high, pulled down
    uart_rx      : in    std_logic;     -- B3
    uart_tx      : out   std_logic;     -- C3
    activity_led : out   std_logic;     -- E8 ? driven by port_b(0)
    led          : out   std_logic;  -- L6 ? driven by port_a(0), blink from C
    ow_pin       : inout std_logic  -- 1-Wire bus (4.7 kohm pull-up externally)
  );

end entity pic_top;

architecture rtl of pic_top is

  component prog_rom
    port (
      clk  : in  std_logic;
      rst  : in  std_logic;
      addr : in  std_logic_vector(12 downto 0);
      data : out std_logic_vector(13 downto 0)
    );
  end component;

  constant CLK_FREQ : positive := 50_000_000;

  -- Power-on reset: hold reset for 64 cycles then release
  signal rst_cnt : unsigned(5 downto 0) := (others => '0');
  signal reset   : std_logic            := '1';

  signal pc       : std_logic_vector(12 downto 0);
  signal opcode   : std_logic_vector(13 downto 0);
  signal port_a   : std_logic_vector(7 downto 0);
  signal port_b   : std_logic_vector(7 downto 0);
  signal work_reg : std_logic_vector(7 downto 0);
  signal status   : std_logic_vector(2 downto 0);

begin

  por : process(clk)
  begin
    if rising_edge(clk) then
      if reset_btn = '1' then
        rst_cnt <= (others => '0');     -- re-arm counter while button held
        reset   <= '1';
      elsif rst_cnt(5) = '0' then
        rst_cnt <= rst_cnt + 1;
        reset   <= '1';
      else
        reset <= '0';
      end if;
    end if;
  end process por;

  activity_led <= port_b(0);
  led          <= port_a(0);

  rom : prog_rom
    port map (
      clk  => clk,
      addr => pc,
      data => opcode,
      rst  => reset
      );

  cpu : entity work.PIC
    generic map (
      CLK_FREQ => CLK_FREQ
      )
    port map (
      clk             => clk,
      reset           => reset,
      opcode          => opcode,
      program_counter => pc,
      work_reg        => work_reg,
      status          => status,
      port_a          => port_a,
      port_b          => port_b,
      uart_tx         => uart_tx,
      uart_rx         => uart_rx,
      ow_pin          => ow_pin
      );

end architecture rtl;