#+TITLE: DE2 example projects
#+TODO: TODO STARTED BLOCKED FIXME | DONE

* description
Some scripts and simple example/educational hardware descriptions in
Verilog for the Altera DE2 development board (Cyclone II).  

* tasks
*** TODO script for project generation and location assignment
for Quartus II, old Java software... :D
*** TODO ALU
- maybe floating point calculations?
- bigint?
- something interesting
*** STARTED numerically controlled oscillator
**** DONE clock divisions for CODEC
**** DONE i2c controller
**** DONE i2c communication with audio CODEC
read address: 0x34
- SCLK | J18 | I2C Data
- SDAT | H18 | I2C Clock
- DACDAT | A4 | CODEC DAC data
- XCK | A5 | CODEC chip clock
- BCLK | B4 | CODEC bitstream clock
- https://github.com/Reenforcements/VerilogDE2115AudioFilters
- https://www.youtube.com/watch?v=_WdMaqUiZeA&list=PLIA9XWvqXXMzzO0g6bZTEtjTBv6sbKYpN
**** DONE i2s bitstream
**** STARTED hardware and simulation testing
***** FIXME odd reset behaviour
The tone only plays when reset is held down. Seems like all NCO loop
behaviour only happens when reset held down also (seven segment display)


* some resources
- https://github.com/simon-77/Install-Quartus-and-ModelSim-on-Linux-openSUSE
  * some tips on UDEV rules for the USB blaster
- https://github.com/snwjas/DE2-Electric-Timer/blob/master/electricTimer/electricTimer.qsf
- https://github.com/tymonx/logic
- https://github.com/Reenforcements/VerilogDE2115AudioFilters