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| author | Väinö Kauppila <vaino@vke.fi> | 2026-04-20 18:21:28 +0300 |
|---|---|---|
| committer | Väinö Kauppila <vaino@vke.fi> | 2026-04-20 18:21:28 +0300 |
| commit | 7af8820d2dbd441f95cb5c8bde74e4649878383c (patch) | |
| tree | 46775e7fc08137d8d40a69d70be4e2d76265cc66 /Makefile.inner | |
| parent | bada76e705a4219fe2da27bb59c32dbdd0601514 (diff) | |
| download | vhdl_pic-7af8820d2dbd441f95cb5c8bde74e4649878383c.tar.gz vhdl_pic-7af8820d2dbd441f95cb5c8bde74e4649878383c.zip | |
prog rom generation using Amaranth
Diffstat (limited to 'Makefile.inner')
| -rw-r--r-- | Makefile.inner | 29 |
1 files changed, 20 insertions, 9 deletions
diff --git a/Makefile.inner b/Makefile.inner index aa6572a..b1fe730 100644 --- a/Makefile.inner +++ b/Makefile.inner @@ -9,8 +9,12 @@ CST = primer25k.cst MODULE = -m ghdl STD = --std=08 -# Synthesizable sources (no testbenches, no VHDL file-I/O packages) -SYN_FILES = \ +# Synthesizable sources + +SYN_VERILOG_FILES = \ + $(HDL_DIR)/prog_rom.v + +SYN_VHDL_FILES = \ $(HDL_DIR)/common.vhd \ $(HDL_DIR)/decoder.vhd \ $(HDL_DIR)/fifo.vhd \ @@ -22,7 +26,6 @@ SYN_FILES = \ $(HDL_DIR)/dpram.vhd \ $(HDL_DIR)/state_machine.vhd \ $(HDL_DIR)/PIC.vhd \ - $(HDL_DIR)/prog_rom.vhd \ $(HDL_DIR)/pic_top.vhd # Simulation adds the hex-reader package and testbenches @@ -50,9 +53,13 @@ $(BUILD): mkdir -p $@ # Synthesize -$(BUILD)/$(TOP).json: $(SYN_FILES) | $(BUILD) - ghdl -a $(STD) --workdir=$(BUILD) $(SYN_FILES) - yosys $(MODULE) -p "ghdl $(STD) --workdir=$(BUILD) $(TOP); synth_gowin -json $@ -family gw5a -nolutram" +$(BUILD)/$(TOP).json: $(SYN_VHDL_FILES) $(SYN_VERILOG_FILES) | $(BUILD) + ghdl -a $(STD) --workdir=$(BUILD) $(SYN_VHDL_FILES) + yosys $(MODULE) -p " \ + ghdl $(STD) --workdir=$(BUILD) $(TOP); \ + read_verilog $(SYN_VERILOG_FILES); \ + synth_gowin -json $@ -family gw5a -nolutram \ + " # Place and route $(BUILD)/$(TOP)_pnr.json: $(BUILD)/$(TOP).json $(CST) @@ -72,9 +79,13 @@ sim: $(SIM_FILES) $(TB_FILES) | $(BUILD) ghdl -e $(STD) --workdir=$(BUILD) -o $(BUILD)/tb_pic tb_pic $(BUILD)/tb_pic --vcd=$(BUILD)/tb_pic.vcd -$(BUILD)/pic_top.dot: $(SYN_FILES) | $(BUILD) - ghdl -a $(STD) --workdir=$(BUILD) $(SYN_FILES) - yosys $(MODULE) -p "ghdl $(STD) --workdir=$(BUILD) $(TOP); show -format dot -prefix $(BUILD)/pic_top" +$(BUILD)/pic_top.dot: $(SYN_VHDL_FILES) $(SYN_VERILOG_FILES) | $(BUILD) + ghdl -a $(STD) --workdir=$(BUILD) $(SYN_VHDL_FILES) + yosys $(MODULE) -p " \ + ghdl $(STD) --workdir=$(BUILD) $(TOP); \ + read_verilog $(SYN_VERILOG_FILES); \ + show -format dot -prefix $(BUILD)/pic_top \ + " $(BUILD)/uart.dot: $(HDL_DIR)/fifo.vhd $(HDL_DIR)/uart.vhd | $(BUILD) ghdl -a $(STD) --workdir=$(BUILD) $(HDL_DIR)/fifo.vhd $(HDL_DIR)/uart.vhd |