interrupts working now with timer

1 files changed, 7 insertions, 12 deletions

diff --git a/fw/timer0_test.c b/fw/timer0_test.c
index ef5e622..658cd79 100644
--- a/fw/timer0_test.c
+++ b/fw/timer0_test.c
@@ -6,21 +6,18 @@ __sfr __at(0x70) UART_TX;
 __sfr __at(0x72) UART_STATUS;
 
 /*
+ * OPTION_REG, T0IF, T0IE, GIE are all provided by pic16f84a.h.
  * OPTION_REG 0x07: T0CS=0 (Fosc/4), PSA=0, PS=111 (1:256)
  * At 50 MHz: overflow every 256*256 / (50M/4) = 5.24 ms → ~191 ovf/sec
  */
-#define STATUS_RP0   0x20
-#define T0IF         0x04   /* INTCON bit 2 */
-#define T0IE         0x20   /* INTCON bit 5 */
-#define GIE          0x80   /* INTCON bit 7 */
 #define OVF_PER_SEC  191
 
 static volatile uint8_t ovf_count = 0;
 
 void isr(void) __interrupt(0) {
-    if (INTCON & T0IF) {
+    if (INTCON & 0x04) {        /* T0IF = bit 2 */
         ovf_count++;
-        INTCON &= ~T0IF;
+        INTCON &= ~(uint8_t)0x04;
     }
 }
 
@@ -48,13 +45,11 @@ static void print_uint8(uint8_t v) {
 void main(void) {
     uint8_t seconds = 0;
 
-    /* Configure OPTION_REG (bank 1, same 7-bit addr as TMR0) */
-    STATUS |= STATUS_RP0;
-    TMR0 = 0x07;
-    STATUS &= ~STATUS_RP0;
+    /* T0CS=0 (Fosc/4), PSA=0, PS=111 (1:256 prescaler) */
+    OPTION_REG = 0x07;
 
     TMR0 = 0;
-    INTCON = T0IE | GIE;    /* enable Timer0 overflow interrupt */
+    INTCON = 0xa0;    /* T0IE | GIE */
 
     uart_puts("\x1B[2J\x1B[H");
     uart_puts("Timer0 test\r\n");
@@ -62,7 +57,7 @@ void main(void) {
 
     while (1) {
         ovf_count = 0;
-        while (ovf_count < OVF_PER_SEC);   /* ISR bumps ovf_count */
+        while (ovf_count < OVF_PER_SEC);
 
         uart_puts("t = ");
         print_uint8(seconds);