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| author | Väinö Kauppila <vaino@vke.fi> | 2026-04-20 18:21:28 +0300 |
|---|---|---|
| committer | Väinö Kauppila <vaino@vke.fi> | 2026-04-20 18:21:28 +0300 |
| commit | 7af8820d2dbd441f95cb5c8bde74e4649878383c (patch) | |
| tree | 46775e7fc08137d8d40a69d70be4e2d76265cc66 /hdl/PIC.vhd | |
| parent | bada76e705a4219fe2da27bb59c32dbdd0601514 (diff) | |
| download | vhdl_pic-7af8820d2dbd441f95cb5c8bde74e4649878383c.tar.gz vhdl_pic-7af8820d2dbd441f95cb5c8bde74e4649878383c.zip | |
prog rom generation using Amaranth
Diffstat (limited to 'hdl/PIC.vhd')
| -rw-r--r-- | hdl/PIC.vhd | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/hdl/PIC.vhd b/hdl/PIC.vhd index 7471add..20c0bb2 100644 --- a/hdl/PIC.vhd +++ b/hdl/PIC.vhd @@ -14,7 +14,6 @@ entity PIC is opcode : in std_logic_vector(13 downto 0); program_counter : out std_logic_vector(12 downto 0) := (others => '0'); - instruction_return : out std_logic := '0'; work_reg : out std_logic_vector(7 downto 0) := (others => '0'); status : out std_logic_vector(2 downto 0) := (others => '0'); port_a : out std_logic_vector(7 downto 0) := (others => '0'); @@ -47,7 +46,6 @@ architecture rtl of PIC is signal sm_data : std_logic_vector(7 downto 0); signal sm_pc : std_logic_vector(12 downto 0); signal we_w : std_logic; - signal instr_ret : std_logic; signal alu_status : std_logic_vector(2 downto 0); signal use_literal : std_logic; @@ -92,7 +90,6 @@ begin work_reg <= W; program_counter <= sm_pc; - instruction_return <= instr_ret; status <= alu_status; -- banking: RP0 (STATUS bit 5) selects bank 0 or bank 1 @@ -125,7 +122,6 @@ begin we_mem => mem_we, re_mem => mem_re, we_w => we_w, - instr_ret => instr_ret, bit_select => bit_select, data => sm_data, pc => sm_pc, |