remove redundant clock input from verilog generator

1 files changed, 12 insertions, 18 deletions

diff --git a/hdl/prog_rom.v b/hdl/prog_rom.v
index 03b8d9e..ae35289 100644
--- a/hdl/prog_rom.v
+++ b/hdl/prog_rom.v
@@ -1,31 +1,26 @@
 /* Generated by Yosys 0.63+89 (git sha1 de99d67bb, clang++ 18.1.8 -fPIC -O3) */
 
 (* top = 0  *)
-(* src = "/workspace/hdl/rom.py:39" *)
+(* src = "/workspace/hdl/rom.py:34" *)
 (* generator = "Amaranth" *)
-module prog_rom(addr, \clk$3 , rst, data, clk);
-  (* src = "/workspace/hdl/rom.py:42" *)
-  input [12:0] addr;
-  wire [12:0] addr;
+module prog_rom(clk, rst, data, addr);
   (* src = "/usr/local/lib/python3.11/dist-packages/amaranth/hdl/_ir.py:283" *)
-  input \clk$3 ;
-  wire \clk$3 ;
+  input clk;
+  wire clk;
   (* src = "/usr/local/lib/python3.11/dist-packages/amaranth/hdl/_ir.py:283" *)
   input rst;
   wire rst;
-  (* src = "/workspace/hdl/rom.py:46" *)
+  (* src = "/workspace/hdl/rom.py:40" *)
   output [13:0] data;
   wire [13:0] data;
-  (* src = "/workspace/hdl/rom.py:41" *)
-  input clk;
-  wire clk;
-  (* src = "/usr/local/lib/python3.11/dist-packages/amaranth/hdl/_ir.py:283" *)
-  wire \clk$7 ;
-  (* src = "/workspace/hdl/rom.py:46" *)
+  (* src = "/workspace/hdl/rom.py:36" *)
+  input [12:0] addr;
+  wire [12:0] addr;
+  (* src = "/workspace/hdl/rom.py:40" *)
   wire [11:0] mem_r_addr;
-  (* src = "/workspace/hdl/rom.py:46" *)
+  (* src = "/workspace/hdl/rom.py:40" *)
   wire [13:0] mem_r_data;
-  (* src = "/workspace/hdl/rom.py:45" *)
+  (* src = "/workspace/hdl/rom.py:39" *)
   reg [13:0] \U$0  [4095:0];
   initial begin
     \U$0 [0] = 14'h0000;
@@ -4126,11 +4121,10 @@ module prog_rom(addr, \clk$3 , rst, data, clk);
     \U$0 [4095] = 14'h0000;
   end
   reg [13:0] _0_;
-  always @(posedge \clk$3 ) begin
+  always @(posedge clk) begin
     _0_ <= \U$0 [addr[11:0]];
   end
   assign data = _0_;
   assign mem_r_addr = addr[11:0];
   assign mem_r_data = data;
-  assign \clk$7  = \clk$3 ;
 endmodule