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| author | Vaino Kauppila <vaino@vke.fi> | 2026-04-19 12:32:58 +0300 |
|---|---|---|
| committer | Vaino Kauppila <vaino@vke.fi> | 2026-04-19 12:32:58 +0300 |
| commit | eb8643ddbef43547eb7bfe58789a3908926c7258 (patch) | |
| tree | fadfba88a1c71b266b8c67df166a3a6ead6b30d1 /hdl/stack.vhd | |
| parent | 129a1c975dbd0c042576010b1f6eb40d19fc5733 (diff) | |
| download | vhdl_pic-eb8643ddbef43547eb7bfe58789a3908926c7258.tar.gz vhdl_pic-eb8643ddbef43547eb7bfe58789a3908926c7258.zip | |
refactor dir structure, add fib.c
Diffstat (limited to 'hdl/stack.vhd')
| -rw-r--r-- | hdl/stack.vhd | 51 |
1 files changed, 51 insertions, 0 deletions
diff --git a/hdl/stack.vhd b/hdl/stack.vhd new file mode 100644 index 0000000..fd376c0 --- /dev/null +++ b/hdl/stack.vhd @@ -0,0 +1,51 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity stack is + generic ( + DEPTH : positive := 8; + WIDTH : positive := 13 + ); + port ( + clk : in std_logic; + reset : in std_logic; + push : in std_logic; + pop : in std_logic; + din : in std_logic_vector(WIDTH - 1 downto 0); + dout : out std_logic_vector(WIDTH - 1 downto 0) + ); +end entity stack; + +architecture rtl of stack is + + type stack_t is + array (0 to DEPTH - 1) + of std_logic_vector(WIDTH - 1 downto 0); + + signal mem : stack_t + := (others => (others => '0')); + + -- write pointer + signal top : unsigned(2 downto 0) + := (others => '0'); +begin + + dout <= + mem(to_integer(top - 1)) when top /= 0 else (others => '0'); + + stck : process(clk, reset) + begin + if reset = '1' then + top <= (others => '0'); + elsif rising_edge(clk) then + if push = '1' then + mem(to_integer(top)) <= din; + top <= top + 1; + elsif pop = '1' then + top <= top - 1; + end if; + end if; + end process; + +end architecture rtl; |
