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| author | Väinö Kauppila <vaino@vke.fi> | 2026-04-20 15:11:08 +0300 |
|---|---|---|
| committer | Väinö Kauppila <vaino@vke.fi> | 2026-04-20 15:11:08 +0300 |
| commit | b33ebdfd1087bd1de038e23fd256ad5cc6576cfd (patch) | |
| tree | 4d1118c3c7f3a2bc9d283049ea07f6726048ceda /hex2rom.py | |
| parent | 922c620bf0921a60e15e8abe627b3199e7e1e12a (diff) | |
| download | vhdl_pic-b33ebdfd1087bd1de038e23fd256ad5cc6576cfd.tar.gz vhdl_pic-b33ebdfd1087bd1de038e23fd256ad5cc6576cfd.zip | |
4K progmem
Diffstat (limited to 'hex2rom.py')
| -rw-r--r-- | hex2rom.py | 4 |
1 files changed, 2 insertions, 2 deletions
@@ -9,7 +9,7 @@ Usage: import sys import argparse -DEPTH = 1024 +DEPTH = 4096 INST_BITS = 14 def parse_ihex(path): @@ -63,7 +63,7 @@ def render(words): lines.append(' process(clk)') lines.append(' begin') lines.append(' if rising_edge(clk) then') - lines.append(' data <= rom(to_integer(unsigned(addr(9 downto 0))));') + lines.append(' data <= rom(to_integer(unsigned(addr(11 downto 0))));') lines.append(' end if;') lines.append(' end process;') lines.append('end architecture rtl;') |