1 files changed, 81 insertions, 0 deletions
diff --git a/Makefile.inner b/Makefile.inner
new file mode 100644
index 0000000..3184cc3
--- /dev/null
+++ b/Makefile.inner
@@ -0,0 +1,81 @@
+PIC_DIR = PIC
+
+DEVICE  = GW5A-LV25MG121NES
+FAMILY  = GW5A-25A
+TOP     = pic_top
+CST     = primer25k.cst
+
+MODULE  = -m ghdl
+STD     = --std=08
+
+# Synthesizable sources (no testbenches, no VHDL file-I/O packages)
+SYN_FILES = \
+	$(PIC_DIR)/common.vhd \
+	$(PIC_DIR)/decoder.vhd \
+	$(PIC_DIR)/fifo.vhd \
+	$(PIC_DIR)/uart.vhd \
+	$(PIC_DIR)/ALU.vhd \
+	$(PIC_DIR)/stack.vhd \
+	$(PIC_DIR)/dpram.vhd \
+	$(PIC_DIR)/state_machine.vhd \
+	$(PIC_DIR)/PIC.vhd \
+	$(PIC_DIR)/prog_rom.vhd \
+	$(PIC_DIR)/pic_top.vhd
+
+# Simulation adds the hex-reader package and testbenches
+SIM_FILES = \
+	$(PIC_DIR)/common.vhd \
+	$(PIC_DIR)/decoder.vhd \
+	$(PIC_DIR)/hexfile_reader.vhd \
+	$(PIC_DIR)/fifo.vhd \
+	$(PIC_DIR)/uart.vhd \
+	$(PIC_DIR)/ALU.vhd \
+	$(PIC_DIR)/stack.vhd \
+	$(PIC_DIR)/dpram.vhd \
+	$(PIC_DIR)/state_machine.vhd \
+	$(PIC_DIR)/PIC.vhd
+
+TB_FILES = \
+	$(PIC_DIR)/tb_stack.vhd \
+	$(PIC_DIR)/tb_pic.vhd
+
+all: $(TOP).fs
+
+# Synthesize
+$(TOP).json: $(SYN_FILES)
+	ghdl -a $(STD) $(SYN_FILES)
+	yosys $(MODULE) -p "ghdl $(STD) $(TOP); memory_map; synth_gowin -json $@ -family gw5a"
+
+# Place and route
+$(TOP)_pnr.json: $(TOP).json $(CST)
+	nextpnr-himbaechel --json $< --write $@ \
+		--device $(DEVICE) --vopt family=GW5A-25A --vopt cst=$(CST) \
+		--vopt sspi_as_gpio --freq 50 --report $(TOP)_timing.json
+
+# Pack bitstream
+$(TOP).fs: $(TOP)_pnr.json
+	gowin_pack --sspi_as_gpio --cpu_as_gpio -d $(FAMILY) -o $@ $<
+
+sim: $(SIM_FILES) $(TB_FILES)
+	ghdl -a $(STD) $(SIM_FILES) $(TB_FILES)
+	ghdl -e $(STD) tb_stack
+	ghdl -r $(STD) tb_stack
+	ghdl -e $(STD) tb_pic
+	ghdl -r $(STD) tb_pic --vcd=tb_pic.vcd
+
+pic_top.dot: $(SYN_FILES)
+	ghdl -a $(STD) $(SYN_FILES)
+	yosys $(MODULE) -p "ghdl $(STD) $(TOP); show -format dot -prefix pic_top"
+
+uart.dot: $(PIC_DIR)/fifo.vhd $(PIC_DIR)/uart.vhd
+	ghdl -a $(STD) $(PIC_DIR)/fifo.vhd $(PIC_DIR)/uart.vhd
+	yosys $(MODULE) -p "ghdl $(STD) uart; show -format dot -prefix uart"
+
+clean:
+	rm -f $(TOP).json $(TOP)_pnr.json $(TOP).fs $(TOP)_timing.json
+	rm -f pic_top.dot uart.dot
+	rm -f *.o work-obj08.cf e~*.lst
+	rm -f *.vcd
+	rm -f tb_pic tb_stack
+
+.PHONY: all sim clean