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|
HDL_DIR = hdl
BUILD = build
DEVICE = GW5A-LV25MG121NES
FAMILY = GW5A-25A
TOP = pic_top
CST = primer25k.cst
MODULE = -m ghdl
STD = --std=08
# Synthesizable sources
SYN_VERILOG_FILES = \
$(HDL_DIR)/prog_rom.v
SYN_VHDL_FILES = \
$(HDL_DIR)/common.vhd \
$(HDL_DIR)/decoder.vhd \
$(HDL_DIR)/fifo.vhd \
$(HDL_DIR)/uart.vhd \
$(HDL_DIR)/onewire.vhd \
$(HDL_DIR)/timer0.vhd \
$(HDL_DIR)/ALU.vhd \
$(HDL_DIR)/stack.vhd \
$(HDL_DIR)/dpram.vhd \
$(HDL_DIR)/state_machine.vhd \
$(HDL_DIR)/PIC.vhd \
$(HDL_DIR)/pic_top.vhd
# Simulation adds the hex-reader package and testbenches
SIM_FILES = \
$(HDL_DIR)/common.vhd \
$(HDL_DIR)/decoder.vhd \
$(HDL_DIR)/hexfile_reader.vhd \
$(HDL_DIR)/fifo.vhd \
$(HDL_DIR)/uart.vhd \
$(HDL_DIR)/onewire.vhd \
$(HDL_DIR)/timer0.vhd \
$(HDL_DIR)/ALU.vhd \
$(HDL_DIR)/stack.vhd \
$(HDL_DIR)/dpram.vhd \
$(HDL_DIR)/state_machine.vhd \
$(HDL_DIR)/PIC.vhd
TB_FILES = \
$(HDL_DIR)/tb_stack.vhd \
$(HDL_DIR)/tb_pic.vhd
all: $(BUILD)/$(TOP).fs
$(BUILD):
mkdir -p $@
# Synthesize
$(BUILD)/$(TOP).json: $(SYN_VHDL_FILES) $(SYN_VERILOG_FILES) | $(BUILD)
ghdl -a $(STD) --workdir=$(BUILD) $(SYN_VHDL_FILES)
yosys $(MODULE) -p " \
ghdl $(STD) --workdir=$(BUILD) $(TOP); \
read_verilog $(SYN_VERILOG_FILES); \
synth_gowin -json $@ -family gw5a -nolutram \
"
# Place and route
$(BUILD)/$(TOP)_pnr.json: $(BUILD)/$(TOP).json $(CST)
nextpnr-himbaechel --json $< --write $@ \
--device $(DEVICE) --vopt family=GW5A-25A --vopt cst=$(CST) \
--vopt sspi_as_gpio --freq 50 --report $(BUILD)/$(TOP)_timing.json \
--threads $(shell nproc)
# Pack bitstream
$(BUILD)/$(TOP).fs: $(BUILD)/$(TOP)_pnr.json
gowin_pack --sspi_as_gpio --cpu_as_gpio -d $(FAMILY) -o $@ $<
sim: $(SIM_FILES) $(TB_FILES) | $(BUILD)
ghdl -a $(STD) --workdir=$(BUILD) $(SIM_FILES) $(TB_FILES)
ghdl -e $(STD) --workdir=$(BUILD) -o $(BUILD)/tb_stack tb_stack
$(BUILD)/tb_stack
ghdl -e $(STD) --workdir=$(BUILD) -o $(BUILD)/tb_pic tb_pic
$(BUILD)/tb_pic --vcd=$(BUILD)/tb_pic.vcd
$(BUILD)/pic_top.dot: $(SYN_VHDL_FILES) $(SYN_VERILOG_FILES) | $(BUILD)
ghdl -a $(STD) --workdir=$(BUILD) $(SYN_VHDL_FILES)
yosys $(MODULE) -p " \
ghdl $(STD) --workdir=$(BUILD) $(TOP); \
read_verilog $(SYN_VERILOG_FILES); \
show -format dot -prefix $(BUILD)/pic_top \
"
$(BUILD)/uart.dot: $(HDL_DIR)/fifo.vhd $(HDL_DIR)/uart.vhd | $(BUILD)
ghdl -a $(STD) --workdir=$(BUILD) $(HDL_DIR)/fifo.vhd $(HDL_DIR)/uart.vhd
yosys $(MODULE) -p "ghdl $(STD) --workdir=$(BUILD) uart; show -format dot -prefix $(BUILD)/uart"
clean:
rm -rf $(BUILD)
.PHONY: all sim clean
|
