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| author | Väinö Kauppila <vaino@vke.fi> | 2026-04-19 19:02:42 +0300 |
|---|---|---|
| committer | Väinö Kauppila <vaino@vke.fi> | 2026-04-19 19:02:42 +0300 |
| commit | 46e1210381106707c2df7f07c56023eb6b760763 (patch) | |
| tree | 6740a17199f76e2965a511dafcbc7ffb61ceafeb /Makefile.inner | |
| parent | eb8643ddbef43547eb7bfe58789a3908926c7258 (diff) | |
| download | vhdl_pic-46e1210381106707c2df7f07c56023eb6b760763.tar.gz vhdl_pic-46e1210381106707c2df7f07c56023eb6b760763.zip | |
BSRAM progmem. fix Makefile memory command that does not work. add interrupts, bank 1, timer0. Timer0 not tested.
Diffstat (limited to 'Makefile.inner')
| -rw-r--r-- | Makefile.inner | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/Makefile.inner b/Makefile.inner index 957843c..5838b33 100644 --- a/Makefile.inner +++ b/Makefile.inner @@ -15,6 +15,8 @@ SYN_FILES = \ $(HDL_DIR)/decoder.vhd \ $(HDL_DIR)/fifo.vhd \ $(HDL_DIR)/uart.vhd \ + $(HDL_DIR)/onewire.vhd \ + $(HDL_DIR)/timer0.vhd \ $(HDL_DIR)/ALU.vhd \ $(HDL_DIR)/stack.vhd \ $(HDL_DIR)/dpram.vhd \ @@ -30,6 +32,8 @@ SIM_FILES = \ $(HDL_DIR)/hexfile_reader.vhd \ $(HDL_DIR)/fifo.vhd \ $(HDL_DIR)/uart.vhd \ + $(HDL_DIR)/onewire.vhd \ + $(HDL_DIR)/timer0.vhd \ $(HDL_DIR)/ALU.vhd \ $(HDL_DIR)/stack.vhd \ $(HDL_DIR)/dpram.vhd \ @@ -48,7 +52,7 @@ $(BUILD): # Synthesize $(BUILD)/$(TOP).json: $(SYN_FILES) | $(BUILD) ghdl -a $(STD) --workdir=$(BUILD) $(SYN_FILES) - yosys $(MODULE) -p "ghdl $(STD) --workdir=$(BUILD) $(TOP); memory_map; synth_gowin -json $@ -family gw5a" + yosys $(MODULE) -p "ghdl $(STD) --workdir=$(BUILD) $(TOP); synth_gowin -json $@ -family gw5a -nolutram" # Place and route $(BUILD)/$(TOP)_pnr.json: $(BUILD)/$(TOP).json $(CST) |