| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | remove redundant clock input from verilog generator | Väinö Kauppila | 2026-04-20 | 1 | -1/+1 |
| * | refactor dir structure, add fib.c | Vaino Kauppila | 2026-04-19 | 1 | -0/+342 |
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index : vhdl_pic | |
| PIC16F84-compatible CPU in VHDL on a Tang Primer 25K. Plays snake. | root |
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