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authorVäinö Kauppila <vaino@vke.fi>2026-04-20 18:45:38 +0300
committerVäinö Kauppila <vaino@vke.fi>2026-04-20 18:45:38 +0300
commit9dd09eaa88df41057700e59d9abe83fd204f1215 (patch)
treeff148ddc5c39c148b82d8aeec1182841f04f99ab /hdl/hexfile_reader.vhd
parent7af8820d2dbd441f95cb5c8bde74e4649878383c (diff)
downloadvhdl_pic-9dd09eaa88df41057700e59d9abe83fd204f1215.tar.gz
vhdl_pic-9dd09eaa88df41057700e59d9abe83fd204f1215.zip
remove redundant clock input from verilog generator
Diffstat (limited to 'hdl/hexfile_reader.vhd')
-rw-r--r--hdl/hexfile_reader.vhd2
1 files changed, 1 insertions, 1 deletions
diff --git a/hdl/hexfile_reader.vhd b/hdl/hexfile_reader.vhd
index 143a264..8c38ff4 100644
--- a/hdl/hexfile_reader.vhd
+++ b/hdl/hexfile_reader.vhd
@@ -29,7 +29,7 @@ PACKAGE read_intel_hex_pack IS
CONSTANT Inst_bits : INTEGER := 14;
CONSTANT data_bits : INTEGER := 8;
- CONSTANT inst_mem_size : INTEGER := 1024;
+ CONSTANT inst_mem_size : INTEGER := 4096;
TYPE program_array IS ARRAY (0 TO inst_mem_size-1) OF STD_LOGIC_VECTOR(Inst_bits-1 DOWNTO 0);
------------------------------------------------------------------------------